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1 isl54200 usb 2.0 high/full speed multiplexer isl54200 the intersil isl54200 dual 2:1 multiplexer ic is a single supply part that can operate from a single 2.7v to 5.5v supply. it contains two spdt (single pole/double throw) switches configured as a dpdt. the part was designed for switching be tween usb high-speed and usb full-speed sources in portable battery powered products. the 7 normally-closed (nc) fsx switches can swing rail-to-rail and were specifically designed to pass usb full speed data signals (12mbps) that range from 0v to 3.6v. the 4.5 normally-open (no) hsx switches have high bandwidth and low capacitance and were specifically designed to pass usb high speed data signals (480mbps) with minimal distortion. the part can be used in personal media players and other portable battery powered devices that need to switch between a high-speed transceiver and a full- speed transceiver while connected to a single usb host (computer). the digital logic in puts are 1.8v logic compatible when operated with a 2.7v to 3.6v supply. the part has an enable pin to open all switches. it can be used to facilitate proper bus disconnect an d connection when switching between the usb sources. the isl54200 is available in a 10 ld 3mmx3mm tdfn and a small 10 ld 2.1mmx1.6mm tqfn package. it operates over a temperature range of -40c to +85c. features ? high speed (480mbps) and full speed (12mbps) signaling capability per usb 2.0 ? 1.8v logic compatible (2.7v to +3.6v supply) ? enable pin to open all switches ? -3db frequency - hsx switches. . . . . . . . . . . . . . . . . . . . .880mhz - fsx switches . . . . . . . . . . . . . . . . . . . . .550mhz ? crosstalk @ 1mhz . . . . . . . . . . . . . . . . . . -70db ? off isolation @ 100khz . . . . . . . . . . . . . . . -98db ? single supply operation (v dd ) . . . . . 2.7v to 5.5v ? available in ultra-thin tqfn and tdfn packages ? pb-free (rohs compliant) applications* (see page 16) ? mp3 and other personal media players ? cellular/mobile phones ?pda?s ? digital cameras and camcorders related literature* (see page 16) ? technical brief tb363 ?guidelines for handling and processing moisture sensitive surface mount devices (smds)?. ? application note an1330 ?ISL54200EVAL1Z evaluation board user?s manual? application block diagram portable media device isl54200 usb transceiver high-speed usb connector comd1 comd2 in gnd hsd1 hsd2 fsd1 fsd2 v dd en logic controller 4m usb transceiver full-speed vbus d- d+ gnd 3.3v caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2007, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. june 17, 2010 fn6408.2
isl54200 2 fn6408.2 june 17, 2010 pin configurations isl54200 (10 ld tdfn) top view isl54200 (10 ld tqfn) top view note: 1. isl54200 switches shown for in = logic ?0? and en = logic ?1?. ordering information part number (note 5) part marking temp. range (c) package (pb-free) pkg. dwg. # isl54200irz (note 3) 200z -40 to +85 10 ld 3x3 tdfn l10.3x3a isl54200irz-t (note 2, 3) 200z -40 to +85 10 ld 3x3 tdfn tape and reel l10.3x3a isl54200iruz-t (note 2, 4) fm -40 to +85 10 ld 2.1mmx1.6mm tqfn tape and reel l10.2.1x1.6a ISL54200EVAL1Z evaluation board notes: 2. please refer to tb347 for details on reel specifications. 3. these intersil pb-free plastic packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin pl ate plus anneal (e3 te rmination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). inte rsil pb-free products are ms l classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 4. these intersil pb-free plastic packaged products employ special pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 terminat ion finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 5. for moisture sensitivity level (msl), please see device information page for isl54200 . for more information on msl please see techbrief tb363 . vdd in comd2 comd1 hsd2 gnd 1 2 3 4 5 10 9 8 7 6 fsd2 fsd1 en hsd1 logic control 4m pd 1 3 4 hsd1 comd1 fsd1 in en 2 10 5 7 8 hsd2 comd2 fsd2 gnd 9 6 vdd logic control 4m isl54200
isl54200 3 fn6408.2 june 17, 2010 truth table isl54200 en in fsd1, fsd2 hsd1, hsd2 1 0 on off 11offon 0xoffoff logic ?0? when 0.5v, logic ?1? when 1.4v with a 2.7v to 3.6v supply. x = don?t care pin descriptions isl54200 pin no. name function 1 vdd power supply 2 in select logic control input 3 comd1 usb common port 4 comd2 usb common port 5 gnd ground connection 6 fsd2 full speed usb differential port 7 fsd1 full speed usb differential port 8 hsd2 high speed usb differential port 9 hsd1 high speed usb differential port 10 en bus switch enable - pd thermal pad. tie to ground or float (tdfn package only) isl54200
isl54200 4 fn6408.2 june 17, 2010 absolute maximum ratings thermal information vdd to gnd . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.0v input voltages fsd2, fsd1, hsd2, hsd1 (note 6) . - 1v to ((v dd ) +0.3v) in, en (note 6) . . . . . . . . . . . . . . -0.3v to ((v dd ) +0.3v) output voltages comd1, comd2 (note 6) . . . . . . . . . . . . . . . . . -1v to 5v continuous current (hsd2, hsd1, fsd2, fsd1) . . . 40ma peak current (hsd2, hsd1, fsd2, fsd1) (pulsed 1ms, 10% duty cycle, max) . . . . . . . . . 100ma esd rating: hbm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >7kv mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >400v cdm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.4kv latch-up tested per jedec; clas s ii level a . . . . . at +85c thermal resistance (typical) ja (c/w) jc (c/w) 10 ld tqfn (notes 7, 8) . . . . . . . 145 90 10 ld tdfn (notes 9, 10) . . . . . . . 55 16.5 maximum junction temperature (plastic package). . +150c maximum storage temperature range. . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp operating conditions temperature range . . . . . . . . . . . . . . . . . . -40c to +85c v dd supply voltage range . . . . . . . . . . . . . . . 2.7v to 5.5v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. signals on fsd1, fsd2, hsd1, hsd2, comd1, comd2, en, in exceeding v dd or gnd by specified am ount are clamped. limit current to maximum current ratings. 7. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 8. for jc , the ?case temp? location is taken at the package top center. 9. ja is measured in free air with the component mounted on a high effective thermal conductivity test board with ?direct attach? features. see tech brief tb379. 10. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications - 2.7v to 3.6v supply test conditions: v dd = +3.3v, gnd = 0v, v in h = 1.4v, v in l = 0.5v, v enh = 1.4v, v enl = 0.5v, (note 11), unle ss otherwise specified. bold- face limits apply over the operating temperature range, -40c to +85c. parameter test conditions temp (c) min (notes 12, 13) typ max (notes 12, 13) units analog switch characteristics nc switches (fsd1, fsd2) analog signal range, v analog v dd = 3.3v, in = 0v, en = 3.3v full 0 - v dd v on-resistance, r on v dd = 3.3v, in = 0.5v, en = 1.4v, i comx = 40ma, v fsd1 or v fsd2 = 0v to 3.3v, (see figure 4) +25 - 7 10 full - - 15 r on matching between channels, r on v dd = 3.3v, in = 0.5v, en = 1.4v, i comx = 40ma, v fsd1 or v fsd2 = voltage at max r on over signal range of 0v to 3.3v, (note 15) +25 - 0.1 0.35 full - - 0.4 r on flatness, r flat(on) v dd = 3.3v, in = 0.5v, en = 1.4v, i comx = 40ma, v fsd1 or v fsd2 = 0v to 3.3v, (note 14) +25 - 4 6 full - - 8 off leakage current, i fsx(off) v+ = 3.6v, in = 3.6v, en = 0v and 3.6v, v comx = 0.3v, 3v, v fsx = 3v, 0.3v +25 -20 2 20 na full -70 - 70 na on leakage current, i fsx(on) v+ = 3.6v, in = 0v, en = 3.6v, v comx = 0.3v, 3v, v fsx = 0.3v, 3v +25 -20 2 20 na full -70 - 70 na no switches (hsd1, hsd2) analog signal range, v analog v dd = 3.3v, in = 3.3v, en = 3.3v full 0 - v dd v isl54200
isl54200 5 fn6408.2 june 17, 2010 on-resistance, r on v dd = 3.3v, in = 1.4v, en = 1.4v, i comx = 1ma, v hsd2 or v hsd1 = 3.3v (see figure 3) +25 - 20 30 full - - 35 on-resistance, r on v dd = 3.3v, in = 1.4v, en = 1.4v, i comx = 40ma, v hsd2 or v hsd1 = 0v to 400mv (see figure 3) +25 - 4.5 6 full - - 8 r on matching between channels, r on v dd = 3.3v, in = 1.4v, en = 1.4v, i comx = 40ma, v hsd2 or v hsd1 = voltage at max r on , voltage at max r on over signal range of 0v to 400mv (note 15) +25 - 0.01 0.1 full - - 0.5 r on flatness, r flat(on) v dd = 3.3v, in = 1.4v, en = 1.4v, i comx = 40ma, v hsd2 or v hsd1 = 0v to 400mv, (note 14) +25 - 0.4 1 full - - 1.5 off leakage current, i hsd2(off) or i hsd1(off) v dd = 3.6v, in = 0v, en = 0 and 3.6v, v comd1 or v comd2 = 3v, 0.3v, v hsd2 or v hsd1 = 0.3v, 3v +25 -20 2 20 na full -70 - 70 na on leakage current, i hsd2(on) or i hsd1(on) v dd = 3.6v, in = 3.6v, en = 3.6v, v comd1 or v comd2 = 0.3v, 3.0v, v hsd2 or v hsd1 = 0.3v, 3.0v +25 -20 2 20 na full -70 - 70 na dynamic characteristics turn- on ti m e, t on v dd = 3.3v, r l = 45 , c l = 10pf, (see figure 1) +25 - 25 - ns turn-off time, t off v dd = 3.3v, r l = 45 , c l = 10pf, (see figure 1) +25 - 15 - ns break-before-make time delay, t d v dd = 3.3v, r l = 45 , c l = 10pf, (see figure 2) +25 - 7 - ns skew, t skew (hsx switch) v dd = 3.3v, in = 3.3v, en = 3.3v, r l = 45 , c l = 10pf, t r = t f = 720ps at 480mbps, (duty cycle = 50%) (see figure 7) +25 - 50 - ps tot a l j i t t e r, t j (hsx switch) v dd =3.3v, in = 3.3v, en = 3.3v, r l = 45 , c l = 10pf, t r = t f = 720ps at 480mbps +25 - 210 - ps propagation delay, t pd (hsx switch) v dd = 3.3v, in = 3.3v, en = 3.3v, r l = 45 , c l = 10pf, ( see figure 7) +25 - 250 - ps skew, t skew (fsx switch) v dd = 3.3v, in = 0v, en = 3.3v, r l = 39 , c l = 50pf, t r = t f = 12ns at 12mbps, (duty cycle = 50%) (see figure 7) +25 - 0.15 - ns rise / fall time mismatch, t m (fsx switch) v dd = 3.3v, in = 0v, en = 3.3v, r l = 39 , c l = 50pf,t r = t f = 12ns at 12mbps, (duty cycle = 50%) +25 - 10 - % tot a l j i t t e r, t j (fsx switch) v dd = 3.3v, in = 0v, en = 3.3v, r l = 39 , c l = 50pf, t r = t f = 12ns at 12mbps +25 - 1.6 - ns propagation delay, t pd (fsx switch) v dd = 3.3v, in = 0v, en = 3.3v, r l = 39 , c l = 50pf, ( see figure 7) +25 - 0.9 - ns crosstalk v dd = 3.3v, r l = 45 , f = 1mhz (see figure 6) +25 - -70 - db off isolation v dd = 3.3v, r l = 45 , f = 100khz +25 - -98 - db fsx switch -3db bandwidth signal = -10dbm, 1.0vdc offset, r l = 45 , c l = 5pf +25 - 550 - mhz hsx switch -3db bandwidth signal = -10dbm, 0.2vdc offset, r l = 45 , c l = 5pf +25 - 880 - mhz hsx off capacitance, c hsxoff f = 1mhz, v dd = 3.3v, in = 0v, en = 3.3v, v hsd1 or v hsd2 = v comx = 0v, (see figure 5) +25 - 6 - pf electrical specifications - 2.7v to 3.6v supply test conditions: v dd = +3.3v, gnd = 0v, v in h = 1.4v, v in l = 0.5v, v enh = 1.4v, v enl = 0.5v, (note 11), unle ss otherwise specified. bold- face limits apply over the operating temperature range, -40c to +85c. (continued) parameter test conditions temp (c) min (notes 12, 13) typ max (notes 12, 13) units isl54200
isl54200 6 fn6408.2 june 17, 2010 fsx off capacitance, c fsxoff f = 1mhz, v dd = 3.3v, in = 3.3v, en = 3.3v, v fsd1 or v fsd2 = v comx = 0v, (see figure 5) +25 - 9 - pf com on capacitance, c comx(on) f = 1mhz, v dd = 3.3v, in = 3.3v, en = 3.3v, v hsd1 or v hsd2 = v comx = 0v, (see figure 5) +25 - 12 - pf com on capacitance, c comx(on) f = 1mhz, v dd = 3.3v, in = 0v, en = 3.3v, v fsd1 or v fsd2 = v comx = 0v, (see figure 5) +25 - 15 - pf power supply characteristics power supply range, v dd full 2.7 - 5.5 v positive supply current, i dd v dd = 3.6v, in = 0v or 3.6v, en = 0v or 3.6v +25 - 20 60 na full - - 500 na digital input characteristics input voltage low, v inl , v enl v dd = 2.7v to 3.6v full - - 0.5 v input voltage high, v inh , v enh v dd = 2.7v to 3.6v full 1.4 -- v input current, i inl , i enl v dd = 3.6v, in = 0v, en = 0v full - 10 - na input current, i inh v dd = 3.6v, in = 3.6 full - 10 - na input current, i enh v dd = 3.6v, en = 3.6 full - 1 - a notes: 11. v logic = input voltage to perform proper function. 12. the algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 13. parts are 100% tested at +25c. over temperature limits es tablished by characterization and are not production tested. 14. flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 15. r on matching between channels is calculated by subtracting the channel with the highest max r on value from the channel with lowest max r on value, between hsd2 and hsd1 or between fsd2 and fsd1. test circuits and waveforms logic input waveform is inverted for switches that have the opposite logic sense. figure 1a. measurement points repeat test for all switches. c l includes fixture and stray capacitance. figure 1b. test circuit figure 1. switching times electrical specifications - 2.7v to 3.6v supply test conditions: v dd = +3.3v, gnd = 0v, v in h = 1.4v, v in l = 0.5v, v enh = 1.4v, v enl = 0.5v, (note 11), unle ss otherwise specified. bold- face limits apply over the operating temperature range, -40c to +85c. (continued) parameter test conditions temp (c) min (notes 12, 13) typ max (notes 12, 13) units 50% tr < 20ns tf < 20ns toff 90% vinh 0v vinput vinl ton logic input switch input switch output 90% vout v out v (input) r l r l r on + ----------------------- - = switch input vin vout rl cl comx hsx or fsx in 45 10pf gnd vdd en vinput isl54200
isl54200 7 fn6408.2 june 17, 2010 figure 2a. measurement points figure 2b. test circuit figure 2. break-before-make time figure 3. hsx switch r on test circuit figure 4. fsx switch r on test circuit test circuits and waveforms (continued) 90% vinh vinl td logic input switch output 0v vout vin in comx rl cl vout 10pf 45 fsd1 or fsd2 vdd gnd v input c en hsd1 or hsd2 repeat test for all switches. c l includes fixture and stray capacitance. vdd c 1.4v hsx comx in gnd vhsx v1 r on = v1/icomx icomx repeat test for all switches. en 1.4v v dd c 0.5v fsx comx in gnd v fsx v 1 r on = v 1 /40ma 40ma repeat test for all switches. en 1.4v isl54200
isl54200 8 fn6408.2 june 17, 2010 figure 5. capacitance test circuit figure 6. crosstalk test circuit figure 7a. measurement points figure 7b. test circuit figure 7. skew test test circuits and waveforms (continued) vdd c gnd hsx or fsx comx in impedance analyzer vinl or en vinh repeat test for all switches. analyzer vdd c hsx signal generator rl gnd in comx 45 nc comx fsx signal direction through switch is reversed, worst case values are recorded. repeat test for all switches. en vin din+ din- out+ out- 50% 50% 90% 10% 10% 10% 10% 90% 90% 50% 90% 50% t ri t fi t ro t f0 t skew_i t skew_o out+ cl comd1 d2 gnd vdd c d1 comd2 cl out- din+ din- |tro-tri| delay due to switch for rising input and rising output |tfo-tfi| delay due to switch for falling input and falling outpu t |tskew_0| change in skew through the switch for output signa |tskew_i| change in skew through the switch for input signals . 15.8 15.8 143 143 45 45 vin vin en signals. signals. isl54200
isl54200 9 fn6408.2 june 17, 2010 application block diagram detailed description the isl54200 device is a dual single pole/double throw (spdt) analog switch that operates from a single dc power supply in the range of 2.7v to 5.5v. it was designed to function as a dual 2-to-1 multiplexer to select between a usb high-s peed transceiver and a usb full-speed transceiver in portable battery powered products. it is offered in a tdfn package and a small tqfn package for use in mp3 players, cameras, pdas, cellphones, and other personal media players. the device has an enable pin to open all switches. the part consists of two 7 full speed (fsx) switches and two 4.5 high speed (hsx) switches. the fsx switches can swing from 0v to v dd . they were designed to pass usb full speed (12mbps) differential data signals with minimal distortion. the hsx switches have high bandwidth and low capacitance to pass usb high-speed (480mbps) differential data signals with minimal edge and phase distortion. the isl54200 was designed for mp3 players, cameras, cellphones, and other personal media player applications that have both high-speed and full-speed transceivers and need to multiplex between these usb sources to a single usb host (computer). a typical application block diagram of this functionality is shown on page 9. a detailed description of the two types of switches are provided in the following sections. fsx switches (fsd1, fsd2) the two fsx switches (fsd1, fsd2) are bidirectional switches that can pass rail-to-rail signals. when powered with a 3.3v supply, these switches have a nominal r on resistance of 7 over the signal range of 0v to 3.3v. they were specifically designed to pass usb full-speed (12mbps) differential signals and meet the usb 2.0 full- speed signal quality specifications. see figure 8. the fsx switches can also pass usb high speed signals (480mbps) but do not quite meet the usb 2.0 high speed signal quality eye diagram compliance requirement. the maximum signal range for the fsx switches is from -1.5v to v dd . the signal voltage should not be allowed to exceed the v dd voltage rail or go below ground by more than -1.5v. when operated with a 2.7v to 3.6v supply, the fsx switches are active (turned on) whenever the in logic control voltage is 0.5v and the en logic voltage 1.4v. hsx switches (hsd1, hsd2) the two hsx switches (hsd2, hsd1) are bi-directional switches that can pass rail-to-rail signals. when powered with a 3.3v supply, these switches have a nominal r on of 4.5 over the signal range of 0v to 400mv with a r on flatness of 0.4 . the r on matching between the hsd1 and hsd2 switches over this signal range is only 0.01 , ensuring minimal impact by the switches to usb high speed signal transitions. as the signal level increases, the r on switch resistance increases. at signal level of 3.3v, the switch resistance is nominally 20 . the hsx switches were specifically designed to pass usb 2.0 high-speed (480mbps) differential signals typically in the range of 0v to 400mv. they have low capacitance and high bandwidth to pass the usb high-speed signals with minimum edge and phase distortion to meet usb 2.0 high speed signal quality specifications. see figures 9 and 10. the hsx switches can also pass usb full-speed signals (12mbps) with minimal distortion and meet all the usb portable media device isl54200 usb transceiver high-speed usb connector comd1 comd2 in gnd hsd1 hsd2 fsd1 fsd2 vdd en logic controller 4m usb transceiver full-speed vbus d- d+ gnd 3.3v isl54200
isl54200 10 fn6408.2 june 17, 2010 requirements for usb 2.0 full-speed signaling. see figure 11. the maximum signal range for the hsx switches is from -1.5v to v dd . the signal voltage should not be allowed to exceed the v dd voltage rail or go below ground by more than -1.5v. the hsx switches are active (turned on) whenever the in voltage is 1.4v and the en logic voltage 1.4v when operated with a 2.7v to 3.6v supply. isl54200 operation the discussion that follows will discuss using the isl54200 in the typical application shown in the ?application block diagram? on page 9. power the power supply connected at the vdd (pin 1) provides the dc bias voltage required by the isl54200 part for proper operation. the isl54200 can be operated with a vdd voltage in the range of 2.7v to 5.5v. when used in a usb application, the vdd voltage should be kept in the range of 3.0v to 5.5v to ensure you get the proper signal levels for good signal quality. a 0.01f or 0.1f decoupling capacitor should be connected from the vdd pin to ground to filter out any power supply noise from entering the part. the capacitor should be located as close to the vdd pin as possible. logic control the state of the isl54200 device is determined by the voltage at the in pin (pin 2) and the en pin (pin 10). in is only active when the en pin is logic ?1? (high). refer to the ?truth table? on page 3. the en pin is internally pulled low through a 4m resistor to ground. for logic ?0? (low) it can be driven low or allowed to float. the in pin must be driven low or high and cannot be left floating. logic control voltage levels: en = logic ?0? (low) when v en 0.5v or floating. en = logic ?1? (high) when v en 1.4v in = logic ?0? (low) when v in 0.5v. in = logic ?1? (high) when v in 1.4v full-speed mode if the in pin = logic ?0? and the en pin = logic ?1?, the part will be in the full-speed mode. in this mode, the fsd1 and fsd2 switches are on and the hsd1 and hsd2 switches are off (high impedance). in a typical application, v dd will be in the range of 2.8v to 3.6v and will be connected to the battery or ldo of the portable media device. when a computer or usb hub is plugged into the common usb connector and the part is in the full-speed mode, a link will be established between the full-speed driver section of the media player and the computer. the device will be able to transmit and receive data from the computer at a data rate of 12mbps. high-speed mode if the in pin = logic ?1? and the en pin = logic ?1?, the part will go into high-speed mode. in high-speed mode, the hsd1 and hsd2 switches are on and the fsd1 and fsd2 switches are off (high impedance). when a usb cable from a computer or usb hub is connected at the common usb connector and the part is in the high-speed mode, a link will be establis hed between th e high-speed driver section of the media player and the computer. the device will be able to transmit and receive data from the computer at a data rate of 480mbps. all switches off mode if the in pin = logic ?0? or logic ?1? and the en pin = logic ?0?, all of the switches will turn off (high impedance). the all off state can be used to switch between the two usb sections of the media player. when disconnecting from one usb device to the other usb device, you can momentarily put the isl54200 switch in the ?all off? state in order to get the computer to disconnect from the one device so it can properly connect to the other usb device when that channel is turned on. isl54200
isl54200 11 fn6408.2 june 17, 2010 typical performance curves t a = +25c, unless ot herwise specified figure 8. eye pattern: 12mbps usb signal with fsx switches in the signal path time scale (10ns/div) voltage scale (0.5v/div) v dd = 3.3v isl54200
isl54200 12 fn6408.2 june 17, 2010 figure 9. eye pattern with far end mask: 480mbps us b signal with hsx switches in the signal path typical performance curves t a = +25c, unless ot herwise specified (continued) time scale (0.2ns/div) voltage scale (0.1v/div) v dd = 3.3v isl54200
isl54200 13 fn6408.2 june 17, 2010 figure 10. eye pattern with near end mask: 480mbp s usb signal with hsx switches in the signal path typical performance curves t a = +25c, unless ot herwise specified (continued) time scale (0.2ns/div) voltage scale (0.1v/div) v dd = 3.3v isl54200
isl54200 14 fn6408.2 june 17, 2010 figure 11. eye pattern: 12mbps usb signal with hsx switches in the signal path typical performance curves t a = +25c, unless ot herwise specified (continued) time scale (10ns/div) voltage scale (0.5v/div) v dd = 3.3v isl54200
isl54200 15 fn6408.2 june 17, 2010 figure 12. hsx switch on-resistance vs switch voltage figure 13. off-isolation figure 14. crosstalk die characteristics substrate and tdfn thermal pad potential (powered up): gnd transistor count: 98 process: submicron cmos typical performance curves t a = +25c, unless ot herwise specified (continued) r on ( ) v com (v) 0 0.1 0.2 0.3 0. 4 3 3.5 4.0 4.5 5.0 5.5 i com = 40ma +25c +85c -40c v+ = 3.3v 6.0 frequency (mhz) -60 normalized gain (db) 0.01 0.1 1 500 -70 -80 -40 -90 -110 -10 -20 -30 -50 10 0.001 100 v in = 0.2v p-p to 2v p-p r l = 45 frequency (mhz) -60 normalized gain (db) 0.01 0.1 1 500 -70 -80 -40 -90 -110 -10 -20 -30 -50 10 0.001 100 v in = 0.2v p-p to 2v p-p r l = 45 isl54200
isl54200 16 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6408.2 june 17, 2010 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: isl54200 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history date revision change 5/17/10 fn6408.2 updated pb-free bullet in ?features? on page 1 and pb-free notes 3 and 4 in ?ordering information? on page 2 per mark kwoka's new verb iage based on lead fi nish. added tb347 link note 2 to ?ordering information? on page 2 for reel specifications. in ?thermal information? on page 4, added jc for both tdfn and utqfn packages. updated ja for tqfn from 140 to 145. added applicable ja / jc notes 7 through 10. changed ?positive supply current , idd? on page 6 for full temp from: 80na to 500na limit changes required to im prove yield (pcn required) changes to ?l10.2.1x1.6a? on page 17 as follows: converted to new pod format (moved dimensions from ta ble onto drawing) corrected leadframe thickness in detail x from 0.2 ref to 0.125 ref corrected note 4 to read "...between 0. 15mm and 0.30mm...", it previously read "...between .015mm and 0.30mm..." corrected the word "ind entifier" in note 8 to read "identifier". changes to ?l10.3x3a? on page 18 as follows: added typical recommended land pattern put into new data sheet format. changes include: addd ?related literature*(see page 16)? on page 1 added msl note 5 to ?ordering information? on page 2 added "boldface limits apply over the operat ing temperature range, -40c to +85c." to common conditions of "electrical specfications" table beginning on page 4. bolded applicable specs. added ?products? on page 16 added ?revision history? on page 16 updated the ?pin descriptions? on page 3 to show the thermal pad. added latch-up level to ?absolute maximum ratings? on page 4. 7/11/07 fn6408.1 made changes to ?pin descriptions? on page 3 made changes to bandwidth in ?dynamic characteristics? on page 5 on page 11 to page 14, made changes to eye diagram axis labels isl54200
isl54200 17 fn6408.2 june 17, 2010 isl54200 package outline drawing l10.2.1x1.6a 10 lead ultra thin quad flat no-lead plastic package rev 5, 3/10 bottom view detail "x" side view typical recommended land pattern top view 1 2x 0.10 1.60 2.10 b a index area pin 1 1 (6x 0.50 ) (10 x 0.20) (0.10 min.) (0.05 min) 8. (10x 0.60) package (2.00) (0.80) (1.30) (2.50) 0.08 seating plane 0.10 c c c see detail "x" max. 0.55 0 . 125 ref 0-0.05 c 6 9 1 5 6x 0.50 c c 10 x 0.20 4 0.10 m ma b 0.80 pin #1 id 4 10 0.10 min. 0.05 min. 4x 0.20 min. 8. 10x 0.40 outline lead width dimension applies to the metallized terminal and is measured the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. dimensioning and tolerancing conform to asme y14.5m-1994. unless otherwise specified, tolerance : decimal 0.05 1. all dimensions are in millimeters. angles are in degrees. dimensions in ( ) for reference only. between 0.15mm and 0.30mm from the terminal tip. maximum package warpage is 0.05mm. 4. 5. 2. 3. notes: maximum allowable burrs is 0.076mm in all directions. 6. same as jedec mo-255uabd except: 7. no lead-pull-back, min. package thickness = 0.45 not 0.50mm lead length dim. = 0.45mm max. not 0.42mm. 8.
isl54200 18 fn6408.2 june 17, 2010 isl54200 thin dual flat no-lead plastic package (tdfn) // nx (b) section "c-c" for odd terminal/side e cc 5 c l terminal tip (a1) bottom view a 6 area index c c 0.10 0.08 side view 0.10 2x e a b c 0.10 d top view cb 2x 6 8 area index nx l e2 e2/2 ref. e n (nd-1)xe (datum a) (datum b) 5 0.10 8 7 d2 b a c n-1 12 plane seating c a a3 nx b d2/2 nx k l1 9 l m l10.3x3a 10 lead thin dual flat no-lead plastic package symbol millimeters notes min nominal max a 0.70 0.75 0.80 - a1 - - 0.05 - a3 0.20 ref - b 0.20 0.25 0.30 5, 8 d 2.95 3.0 3.05 - d2 2.25 2.30 2.35 7, 8 e 2.95 3.0 3.05 - e2 1.45 1.50 1.55 7, 8 e 0.50 bsc - k 0.25 - - - l 0.25 0.30 0.35 8 n 10 2 nd 5 3 rev. 4 8/09 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd refers to the number of terminals on d. 4. all dimensions are in millim eters. angles are in degrees. 5. dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are provided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. compliant to jedec mo-229-weed-3 except for d2 dimensions. ( 2.90 ) (1.50) ( 10x 0.25) ( 10x 0.50) ( 2.30 ) ( 2.00 ) typical recommended land pattern (8x 0.50) pin 1

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